1. Technical Field
The present invention relates in general to dynamic circuits and, in particular to dynamic logic circuits that include so-called keeper circuits for inhibiting noise-induced and leakage-induced failures. More particularly, the present invention relates to a system and method for reducing switching latency in dynamic logic circuits by minimizing the capacitance and the charge source conflict on the pre-charge node of a dynamic logic circuit.
2. Description of the Related Art
Electronic logic circuits generally fall under one of two categories: static or dynamic. Static circuits include elements that, once set to one of the two binary logic states, will remain in that state indefinitely, until the elements are reset to another state or power is removed from the circuit. Dynamic circuits, on the other hand, include elements that represent the binary logic state to which they are set by dynamically switching a pre-set logic state on a dynamic node.
Since the charge stored within a dynamic circuit dissipates within a few milliseconds, a dynamic logic circuit must include a circuit for precharging the charge storing device at a sufficiently small time interval so that it maintains its logic state prior to a resetting to a different logic state. In accordance with interval timing signals, which are generated by a suitable external clock circuit, in a typical dynamic logic circuit, the charge is delivered and stored during a pre-charge phase and then conditionally discharged during an evaluation phase.
Defective components, charge leakage, electrical noise, and other factors can cause logic circuits to fail, i.e., to produce erroneous results. Dynamic logic is particularly susceptible to failure because any of a large number of leakage and noise mechanisms can undesirably degrade or destroy the stored charge. As described below, so-called weak feedback or xe2x80x9ckeeperxe2x80x9d circuits have been developed to inhibit noise-induced failures in dynamic logic.
As illustrated in FIG. 1, a dynamic logic circuit 100 of the type known in the art as a domino circuit includes a pre-charge device such as P-type field effect transistor (PFET) 102. The gate terminal of PFET 102 is connected to a clock signal input, CLK. The source terminal of PFET 102 is connected to a supply voltage, VDD, and the drain terminal of PFET 102 is connected to a logic network 104 at a dynamic node 106. Logic network 104 typically includes a network of one or more N-type field effect transistors (NFETs) that are source-to-drain connected so as to implement any suitable logic gate function.
Logic network 104 also receives one or more other input signals, IN, that are connected to the gates of the NFETs within logic network 104, which, depending on the topology of its internal NFET network, define the conditions under which logic network 104 discharges dynamic node 106 through an isolation NFET 108. The source terminals of the bottom NFETs of logic network 104 are connected to the drain terminal of isolation NFET 108. As illustrated in FIG. 1, NFET 108 has a clock signal, CLK, applied to its gate terminal and ground (i.e., zero volts with respect to VDD) applied to its source terminal. It is through isolation NFET 108 that logic network 104 discharges dynamic node 106.
As further illustrated in FIG. 1, a PFET 120 charges dynamic node 106 while output OUT1 is at a logic low. In this configuration, PFET 120 acts to protect dynamic node 106 from noise-induced and leakage-induced faults, and is known as a xe2x80x9ckeeperxe2x80x9d device. The source terminal of PFET 120 is connected to VDD while its drain is connected to logic network 104 at dynamic node 106. During the initial portion of an evaluation phase and prior to arrival of new data at IN, OUT1 remains at a logic low state thus enabling PFET 120 to provide charge maintenance at dynamic node 106.
Leakage and noise mechanisms that may adversely affect the performance of dynamic logic circuit 100 may include capacitive coupling to adjacent signals, charge sharing, sub-threshold conduction through NFET logic transistors within logic network 104, and conduction through the NFET logic transistors due to noise on the inputs. If enough of the charge stored on dynamic node 106 is lost due to one or more of these mechanisms, OUT1 may transition to an incorrect state. This error can propagate to other gates (not shown) to which dynamic logic circuit 100 may be coupled and cause erroneous results. To inhibit such charge loss on dynamic node 106, PFET 120 functions as a feedback device to feed back charge to dynamic node 106.
Although the inclusion of a weak feedback circuit in dynamic logic circuit 100 addresses the charge loss problem, it adversely affects the performance of dynamic logic circuit 100 in terms of switching speed. An xe2x80x9cevaluation phasexe2x80x9d of operation within dynamic logic circuit 100 is initiated by a rising edge of CLK (see FIG. 3). If, during an evaluation phase, an evaluation results in a discharge, logic network 104 not only must discharge dynamic node 106, but it must also counteract the charge supplied by PFET 120, thus increasing the time required to discharge dynamic node 106. It is not until OUT1 reaches a sufficiently high level to switch PFET 120 off, that PFET 120 stops conducting, and this delay can adversely affect the operating speed of any circuit that includes dynamic logic circuit 100.
As illustrated in FIG. 1, dynamic logic circuit 100 further includes an inverter 122 that is a complementary metal oxide semiconductor (CMOS) device which includes PFET 124 and an NFET 126. NFET 126 is sometimes referred to as a xe2x80x9cstandbyxe2x80x9d device and is responsible for driving OUT1 low during a pre-charge phase of operation. However, this action of NFET 126 is in conflict with the pull-up action of PFET 124 during the evaluation phase when the logic state at OUT1 is rising and turning off PFET 120. In addition, the gate capacitance of NFET 126 increases the total capacitance of dynamic node 106 which holds a charge that must be discharged (switched) during each evaluation cycle. Standby NFET 126 thus introduces additional switching delay to a data evaluation in addition to that caused by keeper PFET 120 as described above.
In order to minimize the delay caused by standby NFET 126, a designer must consider the tradeoff between the potential impact on performance of providing a minimal sized NFET 126 and the potential impact on reliability of not providing a sufficiently robust NFET 126.
It would therefore be desirable to provide a dynamic circuit that optimizes performance by reducing both of the above-mentioned conflicting conditions, while maintaining reliable operation. These problems are satisfied by the present invention in the manner set forth hereinbelow.
A dynamic circuit having a reduced dynamic node switching latency is disclosed herein. The operating status of the dynamic circuit alternates between a pre-charge phase in which a pre-charge device charges the dynamic node, and an evaluation phase in which the dynamic node is conditionally discharged in accordance with NFET tree inputs. Each evaluation phase may be characterized as including an initial standby interval during which an isolation device is activated but NFET tree inputs have not arrived. Following the standby interval within an evaluation phase is an evaluate interval during which NFET tree inputs may arrive. The standby interval is followed by an evaluate interval in which in response to valid NFET tree inputs, the dynamic node may complete an evaluation discharge. A standby device is utilized to drive an output of the dynamic circuit low during a pre-charge phase and to maintain the output low during a standby interval in which NFET tree inputs do not result in the dynamic node being discharged. The dynamic circuit includes a standby control circuit that disables the standby device during the evaluation interval, resulting in reduced dynamic node switching capacitance. The dynamic circuit may further include a keeper device for maintaining the dynamic node charged during the standby interval of an evaluation phase. A keeper control circuit disables said keeper device during the evaluate interval such that switching latency is further reduced.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.